Logic simulation - PDFSEARCH.IO - Document Search Engine

Logic simulation
Results: 497

#	Item
251	High Speed Serial Link Simulation based on Dynamic Modeling Xiaoqing Dong, Paul Yan, and Moore Mo Huawei Technologies Wenyi Jin and Geoff Zhang Xilinx Inc. Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-02-07 14:28:45 Operations research Simulation Logic simulation
252	DesignCon[removed]High Speed Serial Link Simulation based on Dynamic Modeling Xiaoqing Dong, Huawei Technologies Add to Reading List Source URL: www.xilinx.com Language: English - Date: 2014-02-07 14:28:45 Operations research Simulation software Simulation Signal integrity Logic simulation Scientific modelling Dynamic simulation Electronic engineering Electronic design automation Digital electronics
253	Delivering efficiency Eta Devices is looking for a Senior Digital Hardware Engineer Working at Eta Devices Add to Reading List Source URL: etadevices.com Language: English - Date: 2014-08-08 10:37:58 Logic design Field-programmable gate array Integrated circuit design Verilog Application-specific integrated circuit Embedded system ETA Electrical engineering Logic simulation Electronic engineering Hardware description languages Integrated circuits
254	[removed]Simulation Design Characteristics: Without understanding perspectives.... • Design and conduct poorly run SBL activities Add to Reading List Source URL: www.marquette.edu Language: English - Date: 2014-04-02 19:22:22 Factor analysis Market research Marketing Psychometrics Simulation Q methodology Student engagement Logic simulation Nursing Education Educational psychology Knowledge
255	Design and Implementation of a Coordination Model for Distributed Simulations ∗ Rolf Hennicker, Matthias Ludwig Institut f¨ur Informatik Ludwig-Maximilians-Universit¨at M¨unchen Oettingenstr. 67, D[removed]M¨unchen, Add to Reading List Source URL: www.pst.ifi.lmu.de Language: English - Date: 2006-05-18 12:50:04 Scientific modelling Economic model Logic simulation Scientific modeling Epistemology Ethology Science Computer simulation Aggregate Level Simulation Protocol Electronic design automation Operations research Simulation
256	Optimal Sampling Laws for Stochastically Constrained Simulation Optimization on Finite Sets Susan R. Hunter, Raghu Pasupathy The Grado Department of Industrial and Systems Engineering, Virginia Tech, Blacksburg, VA 24061 Add to Reading List Source URL: scholar.lib.vt.edu Language: English - Date: 2011-03-16 16:23:05 Mathematics Convex optimization Linear programming Constraint Entailment Operations research Logic Mathematical optimization
257	Manufacturing / Printing System Simulator A Design Fest Proposal Designers of real-time embedded software are often faced with a serious problem. The physical system that their software will control is being designed con Add to Reading List Source URL: designfest.acm.org Language: English - Date: 2007-01-15 17:50:20 Electronic design automation Electronics Operations research Simulation Application software Embedded system Communications protocol Software Logic simulation Electronic engineering Digital electronics Logic design
258	Property-Driven Development of a Coordination Model for Distributed Simulations ? Rolf Hennicker and Matthias Ludwig Institut f¨ ur Informatik Ludwig-Maximilians-Universit¨ Add to Reading List Source URL: www.pst.ifi.lmu.de Language: English - Date: 2006-05-18 12:49:36 Simulation Economic model Scientific modelling Logic simulation Model checking Aggregate Level Simulation Protocol Computer simulation Electronic engineering Electronic design automation Operations research
259	Simulation as an experimental design process for emergent systems Paul Andrews1 1 Department Susan Stepney1 Add to Reading List Source URL: www.cs.york.ac.uk Language: English - Date: 2010-04-22 05:54:26 Chaos theory Emergence Scientific terminology Scientific modelling Logic simulation Metaphysics Science Epistemology
260	C-based High Level Synthesis and Verification Tool Set for ASIC・FPGA C-based Design Enables Higher Design Efficiency, Lower Area and Higher Performance of Your Chip (compared to RTL-based design) Add to Reading List Source URL: www.nec.com Language: English - Date: 2012-12-26 01:09:09 Hardware verification languages Logic design SystemC High-level synthesis Logic synthesis VHDL Verilog Field-programmable gate array Logic simulation Electronic engineering Electronic design automation Hardware description languages

UPDATE